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Welcome to Old Skool Anthems
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NATIVE INTERNET WEB RADIO PLAYER PLUGIN FOR SHOUTCAST, ICECAST AND RADIONOMY
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Up grading my graphics card
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<blockquote data-quote="turpieaj" data-source="post: 525937" data-attributes="member: 831"><p><strong><a href="http://www.oldskoolanthemz.com/forum/">http://www.oldskoolanthemz.com/forum/</a>Specifications</strong></p><p></p><ul> <li data-xf-list-type="ul">Form Factor: µATX 24.4 cm. x 22.4 cm Form Factor</li> <li data-xf-list-type="ul">CPU Support<ul> <li data-xf-list-type="ul">Socket -A (Socket 462) for AMD PGA Athlon processor at 3200 MHz and more.</li> <li data-xf-list-type="ul">133/166 and 200 MHz Host bus speed (uses dual clocking to obtain 266, 333 and 400 MHz FSB)</li> </ul></li> <li data-xf-list-type="ul">System Memory<ul> <li data-xf-list-type="ul">Two 184-pin DDR SDRAM DIMM sockets</li> <li data-xf-list-type="ul">Support for single-sided or double-sided DIMMs (DDR266, DDR333 and DDR400)</li> <li data-xf-list-type="ul">Support for up to 2 GB system memory</li> </ul></li> <li data-xf-list-type="ul">KM400A Chipset: VT8378 system controller and VT8235 V-Link south bridge Chipset consisting of the following<ul> <li data-xf-list-type="ul"><ul> <li data-xf-list-type="ul">High performance SMA North Bridge: Integrated VIA Apollo KT400 and graphics accelerator in a single chip</li> <li data-xf-list-type="ul">64-bit Advanced Memory controller supporting DDR333, 266 and 200 SDRAM</li> <li data-xf-list-type="ul">External AGP 8x bus (pins may optionally be used for additional flat panel and flat panel monitor interfaces)</li> <li data-xf-list-type="ul">V-Link south bridge chip includes UltraDMA-133 / 100 / 66 / 33 EIDE, 6 USB 2.0 Ports, AC97 / MC97 link (for audio and modem support), LPC, SMBus, Power Management, and Keyboard / PS2 mouse interfaces plus RTC / CMOS on chip</li> <li data-xf-list-type="ul">2.5 V Core and Mixed 3.3 V / 5 V Tolerant and GTL+I/O</li> <li data-xf-list-type="ul">35 x 35 m HSBGA (Ball Grid Array with Heat Spreader) package with 552 balls</li> </ul></li> <li data-xf-list-type="ul">High Performance Athlon CPU Interface<ul> <li data-xf-list-type="ul">Supports Socket A (Socket 462) AMD Athlon processors</li> <li data-xf-list-type="ul">HSTL-like 1.5 V high-speed transceiver logic signal levels</li> <li data-xf-list-type="ul">Support independent address, data, and snoop interfaces</li> <li data-xf-list-type="ul">200 / 166 / 133 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses</li> <li data-xf-list-type="ul">Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions</li> <li data-xf-list-type="ul">Four-entry command queue to accommodate maximum CPU throughput</li> <li data-xf-list-type="ul">Four-entry probe queue to stores probes from the system to the processor</li> <li data-xf-list-type="ul">Twenty four-entry processor system data and control queue to store system data control commands in two separate read and write buffers for data movement in and out of processor interface</li> <li data-xf-list-type="ul">Supports WC (Write Combining) cycles</li> <li data-xf-list-type="ul">Sleep mode support</li> <li data-xf-list-type="ul">System management interrupt, memory remap and STPCLK mechanism</li> </ul></li> <li data-xf-list-type="ul">High Bandwidth 533 MB / Sec 8-bit -Link Host Controller<ul> <li data-xf-list-type="ul">Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/s</li> <li data-xf-list-type="ul">Operates in 2x, 4x, and 8x modes</li> <li data-xf-list-type="ul">Full duplex commands with separate command / strobe</li> <li data-xf-list-type="ul">Request / Data split transaction</li> <li data-xf-list-type="ul">Configurable outstanding transaction queue for Host to V-Link Client accesses</li> <li data-xf-list-type="ul">Supports Defer / Defer-Reply transactions</li> <li data-xf-list-type="ul">Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles</li> <li data-xf-list-type="ul">Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency</li> <li data-xf-list-type="ul">All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow</li> <li data-xf-list-type="ul">Highly efficient V-Link arbitration with minimum overhead</li> <li data-xf-list-type="ul">All V-Link transactions have predictable cycle length with known command /data duration</li> </ul></li> <li data-xf-list-type="ul">Full Featured Accelerated Graphics Port (AGP) Controller<ul> <li data-xf-list-type="ul">Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling</li> <li data-xf-list-type="ul">AGP v3.0 compliant with 8x transfer mode</li> <li data-xf-list-type="ul">Pseudo-synchronous with the host CPU bus with optimal skew control</li> <li data-xf-list-type="ul">Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)</li> <li data-xf-list-type="ul">AGP pipelined split-transaction long-burst transfers up to 1 GB/s</li> <li data-xf-list-type="ul">Eight level read request queue</li> <li data-xf-list-type="ul">Four level posted-write request queue</li> <li data-xf-list-type="ul">Thirty-two level (quadwords) read data FIFO (256 bytes)</li> <li data-xf-list-type="ul">Sixteen level (quadwords) write data FIFO (128 bytes)</li> <li data-xf-list-type="ul">Intelligent request reordering for maximum AGP bus utilization</li> <li data-xf-list-type="ul">Supports Flush / Fence commands</li> <li data-xf-list-type="ul">Graphics Address Relocation Table (GART)</li> <li data-xf-list-type="ul">One level TLB structure</li> <li data-xf-list-type="ul">Sixteen entry fully associative page table</li> <li data-xf-list-type="ul">LRU replacement scheme</li> <li data-xf-list-type="ul">Independent GART lookup control for host / AGP / PCI master accesses</li> <li data-xf-list-type="ul">Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support</li> </ul></li> <li data-xf-list-type="ul">Advanced System Power Management Support<ul> <li data-xf-list-type="ul">Power down of SDRAM (CKE)</li> <li data-xf-list-type="ul">VTT suspend power plane preserves memory data</li> <li data-xf-list-type="ul">Suspend-to-DRAM and self-refresh power down</li> <li data-xf-list-type="ul">Low-leakage I/O pads</li> <li data-xf-list-type="ul">ACPI 1.0B and PCI Bus Power Management 1.1 compliant</li> </ul></li> <li data-xf-list-type="ul">Advanced High-Performance DDR DRAM Controller<ul> <li data-xf-list-type="ul">Supports DDR333, DDR266, and DDR200 (PC2700, PC2100, and PC1600 DDR SDRAM)</li> <li data-xf-list-type="ul">DRAM interface synchronous with host CPU (200 / 166 / 133 MHz) for most flexible configuration</li> <li data-xf-list-type="ul">DRAM interface may be faster or slower than CPU by 33 MHz (pseudosynchronous with 166/133 MHz FSB clock)</li> <li data-xf-list-type="ul">Concurrent CPU, AGP, and V-Link access</li> <li data-xf-list-type="ul">Clock Enable (CKE) control for DRAM power reduction in high speed systems</li> <li data-xf-list-type="ul">Allows use of either registered or unbuffered memory modules</li> <li data-xf-list-type="ul">Supports 6 banks up to 3 GB DRAMs for registered modules (4 banks up to 2 GB for unbuffered modules) ?Mixed 1M / 2M / 4M / 8M / 16M / 32M / 64M /128M x 8 / 16 / 32 DRAMs</li> <li data-xf-list-type="ul">Flexible row and column addresses 64-bit data width only</li> <li data-xf-list-type="ul">2.5 V SSTL-2 DRAM interface</li> <li data-xf-list-type="ul">Programmable I/O drive capability for MA, MD, and command signals</li> <li data-xf-list-type="ul">Two-bank interleaving for 16 Mbit DRAM support</li> <li data-xf-list-type="ul">Four bank interleaving for 64 MB, 128 MB, 256 MB, 512 MB, and 1GB DRAM support</li> <li data-xf-list-type="ul">Supports maximum 16-bank interleave (i.e. 16 pages open simultaneously); banks are allocated based on LRU</li> <li data-xf-list-type="ul">Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank)</li> <li data-xf-list-type="ul">Four cache lines (16 quadwords) of CPU to DRAM write buffers</li> <li data-xf-list-type="ul">Four cache lines of CPU to DRAM read prefetch buffers</li> <li data-xf-list-type="ul">Read around write capability for non-stalled CPU read</li> <li data-xf-list-type="ul">Speculative DRAM read before snoop result</li> <li data-xf-list-type="ul">Burst read and write operation</li> <li data-xf-list-type="ul">Burst length 4 and 8</li> <li data-xf-list-type="ul">Supports CL 2/2.5 and 1T per command</li> <li data-xf-list-type="ul">1T and 2T command rate which can be specified bank by bank</li> <li data-xf-list-type="ul">Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh)</li> </ul></li> <li data-xf-list-type="ul">Integrated Graphics / Video Accelerator<ul> <li data-xf-list-type="ul">Optimized Shared Memory Architecture (SMA)</li> <li data-xf-list-type="ul">8 / 16 / 32 / 64 MB frame buffer using system memory</li> <li data-xf-list-type="ul">Internal AGP 8x performance</li> <li data-xf-list-type="ul">Separate 128-bit data paths between north bridge and graphics core for pixel data flow and texture / command access</li> <li data-xf-list-type="ul">Graphics engine clocks up to 133 MHz decoupled from memory clock</li> <li data-xf-list-type="ul">High quality DVD video playback</li> <li data-xf-list-type="ul">Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation</li> <li data-xf-list-type="ul">128-bit 2D graphics engine</li> <li data-xf-list-type="ul">128-bit 3D graphics engine</li> <li data-xf-list-type="ul">Floating point triangle setup engine</li> <li data-xf-list-type="ul">3M triangles/second setup engine</li> <li data-xf-list-type="ul">133M pixels/second trilinear fill rate</li> </ul></li> <li data-xf-list-type="ul">Extensive Display Support<ul> <li data-xf-list-type="ul">CRT display interface with 24-bit true-color RAMDAC up to 250 MHz pixel rate with gamma correction capability</li> <li data-xf-list-type="ul">Direct TFT flat panel interface up to 24-bit data width supporting 18, 24, 18 + 18 and 24 + 24 TFT panels or LVDS encoders</li> <li data-xf-list-type="ul">12-bit DVI 1.0-compatible interface for drive of flat panel monitor using external TMDS encoders</li> <li data-xf-list-type="ul">Interface to external TV Encoder for NTSC or PAL TV display</li> <li data-xf-list-type="ul">Support for CRT resolutions up to 1920 x 1440 and panel resolutions up to 1600 x 1200</li> <li data-xf-list-type="ul">Automatic panel power sequencing and VESA DPMS CRT power-down</li> <li data-xf-list-type="ul">Dual view capability where CRT and Flat Panel Monitor can have a different resolution and refresh rate</li> <li data-xf-list-type="ul">Built-in reference voltage generator and monitor sense circuits</li> <li data-xf-list-type="ul">I 2 C SerialBus and DDC Monitor Communications for CRT Plug-and-Play configuration</li> </ul></li> <li data-xf-list-type="ul">Video Support<ul> <li data-xf-list-type="ul">High quality scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and vertical up-scaling and filtering for horizontal and vertical down-scaling)</li> <li data-xf-list-type="ul">Colour space conversion</li> <li data-xf-list-type="ul">Colour enhancement (contrast, hue, saturation, brightness and gamma correction)</li> <li data-xf-list-type="ul">Colour and chroma key support</li> <li data-xf-list-type="ul">Hardware sub-picture blending</li> <li data-xf-list-type="ul">Bob /weave de-interlacing ode and advanced de-interlacing to improve video quality</li> <li data-xf-list-type="ul">PAL /NTSC TV output capability using external TV encoder</li> </ul></li> <li data-xf-list-type="ul">MPEG-2/1 Video Decoder<ul> <li data-xf-list-type="ul">Motion compensation for full speed DVD playback</li> </ul></li> <li data-xf-list-type="ul">2D Hardware Acceleration Features<ul> <li data-xf-list-type="ul">BitBLT (bit block transfer) functions</li> <li data-xf-list-type="ul">Text function</li> <li data-xf-list-type="ul">Bresenha line drawing /style line function</li> <li data-xf-list-type="ul">ROP 3, 256 operation</li> <li data-xf-list-type="ul">Color expansion</li> <li data-xf-list-type="ul">Source and destination color keys</li> <li data-xf-list-type="ul">Transparency mode</li> <li data-xf-list-type="ul">Window clipping</li> <li data-xf-list-type="ul">8, 15 /16, and 32 BPP mode acceleration</li> </ul></li> <li data-xf-list-type="ul">3D Hardware Acceleration Features<ul> <li data-xf-list-type="ul">Microsoft DirectX 7.0 and 8.0 compatible</li> <li data-xf-list-type="ul">OpenGL driver available</li> <li data-xf-list-type="ul">Floating-point setup engine</li> <li data-xf-list-type="ul">Triangle rate up to 3 million triangles per second and Pixel rate up to 133 million pixels per second for 2 texture, depth test and alpha blending</li> <li data-xf-list-type="ul">Hardware back-face culling</li> <li data-xf-list-type="ul">16-bit,32-bit Z test, and 24+8 Z+Stencil test support</li> <li data-xf-list-type="ul">Z-Bias support</li> <li data-xf-list-type="ul">Stipple Test, Line-Pattern test, Texture-Transparence test, Alpha test support</li> <li data-xf-list-type="ul">Edge anti-aliasing support</li> <li data-xf-list-type="ul">Two textures per pass</li> <li data-xf-list-type="ul">Tremendous Texture Format: 16 / 32 BPP ARGB, 1 / 2 / 4 / 8 BPP Luminance, 1 / 2 / 4 / 8 BPP Intensity, 1 / 2 / 4 / 8 BPP Palletized (ARGB), YUV 422 / 420 format</li> <li data-xf-list-type="ul">Texture sizes up to 2048 x 2048</li> <li data-xf-list-type="ul">High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic</li> <li data-xf-list-type="ul">LOD-Bias support</li> <li data-xf-list-type="ul">Vertex Fog and Fog Table</li> <li data-xf-list-type="ul">Specular Lighting</li> <li data-xf-list-type="ul">Alpha Blending</li> <li data-xf-list-type="ul">High quality dithering</li> <li data-xf-list-type="ul">ROP2 support</li> <li data-xf-list-type="ul">Internal full 32-bit ARGB format for high rendering quality</li> <li data-xf-list-type="ul">System balance to achieve high performance</li> </ul></li> </ul></li> <li data-xf-list-type="ul">VT8235 Chipset<ul> <li data-xf-list-type="ul"><ul> <li data-xf-list-type="ul">16-bit V-Link for high bandwidth north bridge data transfer</li> <li data-xf-list-type="ul">Dual channel serial ATA / raid controller</li> <li data-xf-list-type="ul">UltraDMA-133 / 100 / 66 / 33 master mode eide controller</li> <li data-xf-list-type="ul">Integrated fast ethernet and eight port USB 2.0</li> <li data-xf-list-type="ul">Direct sound AC97 audio, keyboard / mouse controller</li> <li data-xf-list-type="ul">RTC, LPC, SMBUS, serial IRQ, plug and play, ACPI</li> <li data-xf-list-type="ul">PC2001 compliant enhanced power management</li> </ul></li> <li data-xf-list-type="ul">High Bandwidth 533 MB/s 8-bit V-Link Client Controller<ul> <li data-xf-list-type="ul">Supports 16-bit 66 MHz V-Link Client interface with total bandwidth of 1066 MB/s</li> <li data-xf-list-type="ul">V-Link operates in 2x, 4x, and 8x modes and either 16-bit or 8-bit (for backwards compatibility)</li> <li data-xf-list-type="ul">Full duplex commands with separate Strobe / Command</li> <li data-xf-list-type="ul">Request / Data split transaction</li> <li data-xf-list-type="ul">Configurable outstanding transaction queue for V-Link Client accesses</li> <li data-xf-list-type="ul">Auto Client Retry to eliminate V-Link Host-Client Retry cycles</li> <li data-xf-list-type="ul">Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link transactions</li> <li data-xf-list-type="ul">for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow</li> <li data-xf-list-type="ul">Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle length</li> <li data-xf-list-type="ul">with known Command / Data duration</li> <li data-xf-list-type="ul">Auto connect / reconnect capability and dynamic stop for minimum power consumption</li> <li data-xf-list-type="ul">Parity checking to insure correct data transfers</li> </ul></li> <li data-xf-list-type="ul">Integrated Peripheral Controllers<ul> <li data-xf-list-type="ul">Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller</li> <li data-xf-list-type="ul">Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability</li> <li data-xf-list-type="ul">Integrated USB 2.0 Controller with four root hubs and eight function ports</li> <li data-xf-list-type="ul">AC-link interface for AC-97 audio codec and modem codec</li> <li data-xf-list-type="ul">HSP modem support</li> <li data-xf-list-type="ul">Integrated DirectSound compatible digital audio controller</li> <li data-xf-list-type="ul">LPC interface for Low Pin Count interface to Super-I/O or ROM</li> </ul></li> <li data-xf-list-type="ul">Integrated Legacy Functions<ul> <li data-xf-list-type="ul">Integrated Keyboard Controller with PS2 mouse support</li> <li data-xf-list-type="ul">Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI</li> <li data-xf-list-type="ul">Integrated DMA, timer, and interrupt controller</li> <li data-xf-list-type="ul">Serial IRQ for docking and non-docking applications</li> <li data-xf-list-type="ul">Fast reset and Gate A20 operation</li> </ul></li> <li data-xf-list-type="ul">UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE (Parallel ATA) Controller<ul> <li data-xf-list-type="ul">Dual channel master mode hard disk controller supporting four Enhanced IDE devices</li> <li data-xf-list-type="ul">Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface</li> <li data-xf-list-type="ul">Increased reliability using UltraDMA-133/100/66 transfer protocols</li> <li data-xf-list-type="ul">Thirty-two levels (double words) of prefetch and write buffers</li> <li data-xf-list-type="ul">Dual DMA engine for concurrent dual channel operation</li> <li data-xf-list-type="ul">Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant</li> <li data-xf-list-type="ul">Full scatter gather capability</li> <li data-xf-list-type="ul">Support ATAPI compliant devices including DVD devices</li> <li data-xf-list-type="ul">Support PCI native and ATA compatibility modes</li> <li data-xf-list-type="ul">Complete software driver support</li> </ul></li> <li data-xf-list-type="ul">Fast Ethernet Controller<ul> <li data-xf-list-type="ul">High performance PCI master interface with scatter / gather and bursting capability</li> <li data-xf-list-type="ul">Standard MII interface to external PHYceiver</li> <li data-xf-list-type="ul">1 / 10 / 100 MHz full and half duplex operation</li> <li data-xf-list-type="ul">Independent 2K byte FIFOs for receive and transmit</li> <li data-xf-list-type="ul">Flexible dynamically loadable EEPROM algorithm</li> <li data-xf-list-type="ul">Physical, Broadcast, and Multicast address filtering using hashing function</li> <li data-xf-list-type="ul">Magic packet and wake-on-address filtering</li> <li data-xf-list-type="ul">Software controllable power down</li> </ul></li> <li data-xf-list-type="ul">Universal Serial Bus Controller<ul> <li data-xf-list-type="ul">USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible</li> <li data-xf-list-type="ul">USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible</li> <li data-xf-list-type="ul">Eighteen level (doublewords) data FIFO with full scatter and gather capability</li> <li data-xf-list-type="ul">Four root hubs and eight function ports</li> <li data-xf-list-type="ul">Integrated physical layer transceivers with optional over-current detection status on USB inputs</li> <li data-xf-list-type="ul">Legacy keyboard and PS/2 mouse support</li> </ul></li> <li data-xf-list-type="ul">Direct Sound Ready AC97 Digital Audio Controller<ul> <li data-xf-list-type="ul">AC-Link access to 4 CODECs (AC97 + AMC97 + MC97)</li> <li data-xf-list-type="ul">Multichannel Audio</li> <li data-xf-list-type="ul">Bus Master Scatter / Gather DMA</li> <li data-xf-list-type="ul">Dedicated read and write channels supporting simultaneous stereo playback and record</li> <li data-xf-list-type="ul">Dedicated read and write channels supporting simultaneous modem receive and transmit</li> <li data-xf-list-type="ul">1 stereo DirectSound channel with source / volume control / mixer</li> <li data-xf-list-type="ul">1 shared FM / SPDIF PCM read channel</li> <li data-xf-list-type="ul">1 dedicated channel supporting multi-channel audio</li> <li data-xf-list-type="ul">32-byte line-buffers for each SGD channel</li> <li data-xf-list-type="ul">Programmable 8-bit / 16-bit mono / stereo PCM data format support</li> <li data-xf-list-type="ul">AC97 2.1 compliant</li> </ul></li> <li data-xf-list-type="ul">System Management Bus Interface<ul> <li data-xf-list-type="ul">Host interface for processor communications</li> <li data-xf-list-type="ul">Slave interface for external SMBus masters</li> </ul></li> <li data-xf-list-type="ul">Concurrent PCI Bus Controller<ul> <li data-xf-list-type="ul">33 MHz operation</li> <li data-xf-list-type="ul">Supports up to six PCI masters</li> <li data-xf-list-type="ul">Peer concurrency</li> <li data-xf-list-type="ul">Concurrent multiple PCI master transactions; i.e. allow PCI masters from both PCI buses active at the same time</li> <li data-xf-list-type="ul">Zero wait state PCI master and slave burst transfer rate</li> <li data-xf-list-type="ul">PCI to system memory data streaming up to 132 MB/s (north bridge data transfer via high speed V-Link)</li> <li data-xf-list-type="ul">PCI master snoop ahead and snoop filtering</li> <li data-xf-list-type="ul">Eight DW of CPU to PCI posted write buffers</li> <li data-xf-list-type="ul">Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities</li> <li data-xf-list-type="ul">Enhanced PCI command optimization (MRL, MRM, MWI, etc.)</li> <li data-xf-list-type="ul">Four lines of post write buffers from PCI masters to DRAM</li> <li data-xf-list-type="ul">Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters</li> <li data-xf-list-type="ul">Delay transaction from PCI master accessing DRAM</li> <li data-xf-list-type="ul">Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)</li> <li data-xf-list-type="ul">Symmetric arbitration between Host/PCI bus for optimized system performance</li> <li data-xf-list-type="ul">Complete steerable PCI interrupts</li> <li data-xf-list-type="ul">PCI-2.2 compliant, 32 bit 3.3 V PCI interface with 5 V tolerant inputs</li> </ul></li> <li data-xf-list-type="ul">Sophisticated PC2001-Compatible Mobile Power Management<ul> <li data-xf-list-type="ul">Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management</li> <li data-xf-list-type="ul">ACPI v2.0 and APM v1.2 Compliant</li> <li data-xf-list-type="ul">CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support</li> <li data-xf-list-type="ul">PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control</li> <li data-xf-list-type="ul">Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,</li> <li data-xf-list-type="ul">suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up</li> <li data-xf-list-type="ul">Multiple suspend power plane controls and suspend status indicators</li> <li data-xf-list-type="ul">One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer</li> <li data-xf-list-type="ul">Normal, doze, sleep, suspend and conserve modes</li> <li data-xf-list-type="ul">Global and local device power control</li> <li data-xf-list-type="ul">System event monitoring with two event classes</li> <li data-xf-list-type="ul">Primary and secondary interrupt differentiation for individual channels</li> <li data-xf-list-type="ul">Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for</li> <li data-xf-list-type="ul">system wake-up</li> <li data-xf-list-type="ul">32 general purpose input ports and 32 output ports</li> <li data-xf-list-type="ul">Multiple internal and external SMI sources for flexible power management models</li> <li data-xf-list-type="ul">Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field</li> <li data-xf-list-type="ul">Thermal alarm on external temperature sensing circuit</li> <li data-xf-list-type="ul">I/O pad leakage control</li> </ul></li> <li data-xf-list-type="ul">Plug and Play Controller<ul> <li data-xf-list-type="ul">PCI interrupts steerable to any interrupt channel</li> <li data-xf-list-type="ul">Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio</li> <li data-xf-list-type="ul">Microsoft Windows XP TM , Windows NT TM , Windows 2000 TM , Windows 98 TM and plug and play BIOS compliant</li> </ul></li> <li data-xf-list-type="ul">Built-in NAND-tree pin scan test capability</li> <li data-xf-list-type="ul">0.22 um, 2.5 V, low power CMOS process</li> <li data-xf-list-type="ul">Single chip 27 x 27 mm, 1.0 mm ball pitch, 539 pin BGA</li> </ul>I/O controller: WINBOND W83697HF I/O Controller with the following features <ul> <li data-xf-list-type="ul">PS/2 Keyboard and Mouse controller</li> <li data-xf-list-type="ul">Floppy disk controller supporting one FDD with 360 KB, 720 KB, 1.2 MB and 1.44 MB</li> <li data-xf-list-type="ul">2 serial ports, both 16C550 Fast UART compatible.</li> <li data-xf-list-type="ul">1 Parallel port supporting SPP (Standard parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Capabilities Port) modes</li> <li data-xf-list-type="ul">1 Fan controller</li> </ul>Audio Chipset: Audio Subsystem for AC'97 processing using the Realtek ALC655 codec <ul> <li data-xf-list-type="ul">DirectSound AC'97 2.2 Audio</li> <li data-xf-list-type="ul">Inputs and Outputs: Stereo inputs for Line-in, CD audio, Auxiliary, mono inputs for microphone</li> <li data-xf-list-type="ul">Mixer Features: mixer with stereo for Line, CD audio, auxiliary, music synthesizer, digital audio (wave files), and mono for microphone and speaker phone</li> <li data-xf-list-type="ul">Features: 3D stereo enhancement for simulated surround, power management support</li> <li data-xf-list-type="ul">Stereo microphone input with integrated preamp for enabling a 2-channel mic array</li> </ul><strong><a href="http://www.oldskoolanthemz.com/forum/">http://www.oldskoolanthemz.com/forum/</a>Connectors</strong><br /> <ul> <li data-xf-list-type="ul">1 AGP slot with integrated retention mechanism</li> <li data-xf-list-type="ul">2 PCI +1 Combo PCI/CNR slot</li> <li data-xf-list-type="ul">1 DB9 serial port (COM A )</li> <li data-xf-list-type="ul">1 Header serial port (COM B )</li> <li data-xf-list-type="ul">1 DB15 VGA port</li> <li data-xf-list-type="ul">1 DB25 parallel port with SPP, ECP, EPP bidirectional modes</li> <li data-xf-list-type="ul">PS/2 keyboard and PS/2 mouse ports (not swappable)</li> <li data-xf-list-type="ul">6 USB 2.0; 2 rear ports + 2 front USB + 2 interne</li> <li data-xf-list-type="ul">1 mono microphone input (Mic-In)</li> <li data-xf-list-type="ul">1 Line-In</li> <li data-xf-list-type="ul">1 Line-Out</li> <li data-xf-list-type="ul">2 IDE connectors</li> <li data-xf-list-type="ul">1 Floppy connector</li> <li data-xf-list-type="ul">Panel connector</li> <li data-xf-list-type="ul">1 RJ45 connector</li> </ul><strong><a href="http://www.oldskoolanthemz.com/forum/">http://www.oldskoolanthemz.com/forum/</a>Winbond BIOS Specifications</strong><br /> <ul> <li data-xf-list-type="ul">Plug and Play</li> <li data-xf-list-type="ul">Advanced Configuration and Power Interface (ACPI) 1.0</li> <li data-xf-list-type="ul">Advanced Power Management (APM) 1.2</li> <li data-xf-list-type="ul">Y2K</li> <li data-xf-list-type="ul">PC 2001</li> <li data-xf-list-type="ul">S3/S1 mode</li> <li data-xf-list-type="ul">Desktop Management Interface (DMI)</li> <li data-xf-list-type="ul">2 Mbits flash device</li> <li data-xf-list-type="ul">Language supported: English</li> </ul></li> </ul></blockquote><p></p>
[QUOTE="turpieaj, post: 525937, member: 831"] [B][URL="http://www.oldskoolanthemz.com/forum/"][/URL]Specifications[/B] [LIST] [*]Form Factor: µATX 24.4 cm. x 22.4 cm Form Factor [*]CPU Support[LIST] [*]Socket -A (Socket 462) for AMD PGA Athlon processor at 3200 MHz and more. [*]133/166 and 200 MHz Host bus speed (uses dual clocking to obtain 266, 333 and 400 MHz FSB)[/LIST] [*]System Memory[LIST] [*]Two 184-pin DDR SDRAM DIMM sockets [*]Support for single-sided or double-sided DIMMs (DDR266, DDR333 and DDR400) [*]Support for up to 2 GB system memory[/LIST] [*]KM400A Chipset: VT8378 system controller and VT8235 V-Link south bridge Chipset consisting of the following[LIST] [*][LIST] [*]High performance SMA North Bridge: Integrated VIA Apollo KT400 and graphics accelerator in a single chip [*]64-bit Advanced Memory controller supporting DDR333, 266 and 200 SDRAM [*]External AGP 8x bus (pins may optionally be used for additional flat panel and flat panel monitor interfaces) [*]V-Link south bridge chip includes UltraDMA-133 / 100 / 66 / 33 EIDE, 6 USB 2.0 Ports, AC97 / MC97 link (for audio and modem support), LPC, SMBus, Power Management, and Keyboard / PS2 mouse interfaces plus RTC / CMOS on chip [*]2.5 V Core and Mixed 3.3 V / 5 V Tolerant and GTL+I/O [*]35 x 35 m HSBGA (Ball Grid Array with Heat Spreader) package with 552 balls[/LIST] [*]High Performance Athlon CPU Interface[LIST] [*]Supports Socket A (Socket 462) AMD Athlon processors [*]HSTL-like 1.5 V high-speed transceiver logic signal levels [*]Support independent address, data, and snoop interfaces [*]200 / 166 / 133 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses [*]Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions [*]Four-entry command queue to accommodate maximum CPU throughput [*]Four-entry probe queue to stores probes from the system to the processor [*]Twenty four-entry processor system data and control queue to store system data control commands in two separate read and write buffers for data movement in and out of processor interface [*]Supports WC (Write Combining) cycles [*]Sleep mode support [*]System management interrupt, memory remap and STPCLK mechanism[/LIST] [*]High Bandwidth 533 MB / Sec 8-bit -Link Host Controller[LIST] [*]Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/s [*]Operates in 2x, 4x, and 8x modes [*]Full duplex commands with separate command / strobe [*]Request / Data split transaction [*]Configurable outstanding transaction queue for Host to V-Link Client accesses [*]Supports Defer / Defer-Reply transactions [*]Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles [*]Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency [*]All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow [*]Highly efficient V-Link arbitration with minimum overhead [*]All V-Link transactions have predictable cycle length with known command /data duration[/LIST] [*]Full Featured Accelerated Graphics Port (AGP) Controller[LIST] [*]Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling [*]AGP v3.0 compliant with 8x transfer mode [*]Pseudo-synchronous with the host CPU bus with optimal skew control [*]Supports SideBand Addressing (SBA) mode (non-multiplexed address / data) [*]AGP pipelined split-transaction long-burst transfers up to 1 GB/s [*]Eight level read request queue [*]Four level posted-write request queue [*]Thirty-two level (quadwords) read data FIFO (256 bytes) [*]Sixteen level (quadwords) write data FIFO (128 bytes) [*]Intelligent request reordering for maximum AGP bus utilization [*]Supports Flush / Fence commands [*]Graphics Address Relocation Table (GART) [*]One level TLB structure [*]Sixteen entry fully associative page table [*]LRU replacement scheme [*]Independent GART lookup control for host / AGP / PCI master accesses [*]Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support[/LIST] [*]Advanced System Power Management Support[LIST] [*]Power down of SDRAM (CKE) [*]VTT suspend power plane preserves memory data [*]Suspend-to-DRAM and self-refresh power down [*]Low-leakage I/O pads [*]ACPI 1.0B and PCI Bus Power Management 1.1 compliant[/LIST] [*]Advanced High-Performance DDR DRAM Controller[LIST] [*]Supports DDR333, DDR266, and DDR200 (PC2700, PC2100, and PC1600 DDR SDRAM) [*]DRAM interface synchronous with host CPU (200 / 166 / 133 MHz) for most flexible configuration [*]DRAM interface may be faster or slower than CPU by 33 MHz (pseudosynchronous with 166/133 MHz FSB clock) [*]Concurrent CPU, AGP, and V-Link access [*]Clock Enable (CKE) control for DRAM power reduction in high speed systems [*]Allows use of either registered or unbuffered memory modules [*]Supports 6 banks up to 3 GB DRAMs for registered modules (4 banks up to 2 GB for unbuffered modules) ?Mixed 1M / 2M / 4M / 8M / 16M / 32M / 64M /128M x 8 / 16 / 32 DRAMs [*]Flexible row and column addresses 64-bit data width only [*]2.5 V SSTL-2 DRAM interface [*]Programmable I/O drive capability for MA, MD, and command signals [*]Two-bank interleaving for 16 Mbit DRAM support [*]Four bank interleaving for 64 MB, 128 MB, 256 MB, 512 MB, and 1GB DRAM support [*]Supports maximum 16-bank interleave (i.e. 16 pages open simultaneously); banks are allocated based on LRU [*]Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank) [*]Four cache lines (16 quadwords) of CPU to DRAM write buffers [*]Four cache lines of CPU to DRAM read prefetch buffers [*]Read around write capability for non-stalled CPU read [*]Speculative DRAM read before snoop result [*]Burst read and write operation [*]Burst length 4 and 8 [*]Supports CL 2/2.5 and 1T per command [*]1T and 2T command rate which can be specified bank by bank [*]Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh)[/LIST] [*]Integrated Graphics / Video Accelerator[LIST] [*]Optimized Shared Memory Architecture (SMA) [*]8 / 16 / 32 / 64 MB frame buffer using system memory [*]Internal AGP 8x performance [*]Separate 128-bit data paths between north bridge and graphics core for pixel data flow and texture / command access [*]Graphics engine clocks up to 133 MHz decoupled from memory clock [*]High quality DVD video playback [*]Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation [*]128-bit 2D graphics engine [*]128-bit 3D graphics engine [*]Floating point triangle setup engine [*]3M triangles/second setup engine [*]133M pixels/second trilinear fill rate[/LIST] [*]Extensive Display Support[LIST] [*]CRT display interface with 24-bit true-color RAMDAC up to 250 MHz pixel rate with gamma correction capability [*]Direct TFT flat panel interface up to 24-bit data width supporting 18, 24, 18 + 18 and 24 + 24 TFT panels or LVDS encoders [*]12-bit DVI 1.0-compatible interface for drive of flat panel monitor using external TMDS encoders [*]Interface to external TV Encoder for NTSC or PAL TV display [*]Support for CRT resolutions up to 1920 x 1440 and panel resolutions up to 1600 x 1200 [*]Automatic panel power sequencing and VESA DPMS CRT power-down [*]Dual view capability where CRT and Flat Panel Monitor can have a different resolution and refresh rate [*]Built-in reference voltage generator and monitor sense circuits [*]I 2 C SerialBus and DDC Monitor Communications for CRT Plug-and-Play configuration[/LIST] [*]Video Support[LIST] [*]High quality scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and vertical up-scaling and filtering for horizontal and vertical down-scaling) [*]Colour space conversion [*]Colour enhancement (contrast, hue, saturation, brightness and gamma correction) [*]Colour and chroma key support [*]Hardware sub-picture blending [*]Bob /weave de-interlacing ode and advanced de-interlacing to improve video quality [*]PAL /NTSC TV output capability using external TV encoder[/LIST] [*]MPEG-2/1 Video Decoder[LIST] [*]Motion compensation for full speed DVD playback[/LIST] [*]2D Hardware Acceleration Features[LIST] [*]BitBLT (bit block transfer) functions [*]Text function [*]Bresenha line drawing /style line function [*]ROP 3, 256 operation [*]Color expansion [*]Source and destination color keys [*]Transparency mode [*]Window clipping [*]8, 15 /16, and 32 BPP mode acceleration[/LIST] [*]3D Hardware Acceleration Features[LIST] [*]Microsoft DirectX 7.0 and 8.0 compatible [*]OpenGL driver available [*]Floating-point setup engine [*]Triangle rate up to 3 million triangles per second and Pixel rate up to 133 million pixels per second for 2 texture, depth test and alpha blending [*]Hardware back-face culling [*]16-bit,32-bit Z test, and 24+8 Z+Stencil test support [*]Z-Bias support [*]Stipple Test, Line-Pattern test, Texture-Transparence test, Alpha test support [*]Edge anti-aliasing support [*]Two textures per pass [*]Tremendous Texture Format: 16 / 32 BPP ARGB, 1 / 2 / 4 / 8 BPP Luminance, 1 / 2 / 4 / 8 BPP Intensity, 1 / 2 / 4 / 8 BPP Palletized (ARGB), YUV 422 / 420 format [*]Texture sizes up to 2048 x 2048 [*]High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic [*]LOD-Bias support [*]Vertex Fog and Fog Table [*]Specular Lighting [*]Alpha Blending [*]High quality dithering [*]ROP2 support [*]Internal full 32-bit ARGB format for high rendering quality [*]System balance to achieve high performance[/LIST][/LIST] [*]VT8235 Chipset[LIST] [*][LIST] [*]16-bit V-Link for high bandwidth north bridge data transfer [*]Dual channel serial ATA / raid controller [*]UltraDMA-133 / 100 / 66 / 33 master mode eide controller [*]Integrated fast ethernet and eight port USB 2.0 [*]Direct sound AC97 audio, keyboard / mouse controller [*]RTC, LPC, SMBUS, serial IRQ, plug and play, ACPI [*]PC2001 compliant enhanced power management[/LIST] [*]High Bandwidth 533 MB/s 8-bit V-Link Client Controller[LIST] [*]Supports 16-bit 66 MHz V-Link Client interface with total bandwidth of 1066 MB/s [*]V-Link operates in 2x, 4x, and 8x modes and either 16-bit or 8-bit (for backwards compatibility) [*]Full duplex commands with separate Strobe / Command [*]Request / Data split transaction [*]Configurable outstanding transaction queue for V-Link Client accesses [*]Auto Client Retry to eliminate V-Link Host-Client Retry cycles [*]Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link transactions [*]for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow [*]Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle length [*]with known Command / Data duration [*]Auto connect / reconnect capability and dynamic stop for minimum power consumption [*]Parity checking to insure correct data transfers[/LIST] [*]Integrated Peripheral Controllers[LIST] [*]Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller [*]Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability [*]Integrated USB 2.0 Controller with four root hubs and eight function ports [*]AC-link interface for AC-97 audio codec and modem codec [*]HSP modem support [*]Integrated DirectSound compatible digital audio controller [*]LPC interface for Low Pin Count interface to Super-I/O or ROM[/LIST] [*]Integrated Legacy Functions[LIST] [*]Integrated Keyboard Controller with PS2 mouse support [*]Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI [*]Integrated DMA, timer, and interrupt controller [*]Serial IRQ for docking and non-docking applications [*]Fast reset and Gate A20 operation[/LIST] [*]UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE (Parallel ATA) Controller[LIST] [*]Dual channel master mode hard disk controller supporting four Enhanced IDE devices [*]Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface [*]Increased reliability using UltraDMA-133/100/66 transfer protocols [*]Thirty-two levels (double words) of prefetch and write buffers [*]Dual DMA engine for concurrent dual channel operation [*]Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant [*]Full scatter gather capability [*]Support ATAPI compliant devices including DVD devices [*]Support PCI native and ATA compatibility modes [*]Complete software driver support[/LIST] [*]Fast Ethernet Controller[LIST] [*]High performance PCI master interface with scatter / gather and bursting capability [*]Standard MII interface to external PHYceiver [*]1 / 10 / 100 MHz full and half duplex operation [*]Independent 2K byte FIFOs for receive and transmit [*]Flexible dynamically loadable EEPROM algorithm [*]Physical, Broadcast, and Multicast address filtering using hashing function [*]Magic packet and wake-on-address filtering [*]Software controllable power down[/LIST] [*]Universal Serial Bus Controller[LIST] [*]USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible [*]USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible [*]Eighteen level (doublewords) data FIFO with full scatter and gather capability [*]Four root hubs and eight function ports [*]Integrated physical layer transceivers with optional over-current detection status on USB inputs [*]Legacy keyboard and PS/2 mouse support[/LIST] [*]Direct Sound Ready AC97 Digital Audio Controller[LIST] [*]AC-Link access to 4 CODECs (AC97 + AMC97 + MC97) [*]Multichannel Audio [*]Bus Master Scatter / Gather DMA [*]Dedicated read and write channels supporting simultaneous stereo playback and record [*]Dedicated read and write channels supporting simultaneous modem receive and transmit [*]1 stereo DirectSound channel with source / volume control / mixer [*]1 shared FM / SPDIF PCM read channel [*]1 dedicated channel supporting multi-channel audio [*]32-byte line-buffers for each SGD channel [*]Programmable 8-bit / 16-bit mono / stereo PCM data format support [*]AC97 2.1 compliant[/LIST] [*]System Management Bus Interface[LIST] [*]Host interface for processor communications [*]Slave interface for external SMBus masters[/LIST] [*]Concurrent PCI Bus Controller[LIST] [*]33 MHz operation [*]Supports up to six PCI masters [*]Peer concurrency [*]Concurrent multiple PCI master transactions; i.e. allow PCI masters from both PCI buses active at the same time [*]Zero wait state PCI master and slave burst transfer rate [*]PCI to system memory data streaming up to 132 MB/s (north bridge data transfer via high speed V-Link) [*]PCI master snoop ahead and snoop filtering [*]Eight DW of CPU to PCI posted write buffers [*]Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities [*]Enhanced PCI command optimization (MRL, MRM, MWI, etc.) [*]Four lines of post write buffers from PCI masters to DRAM [*]Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters [*]Delay transaction from PCI master accessing DRAM [*]Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks) [*]Symmetric arbitration between Host/PCI bus for optimized system performance [*]Complete steerable PCI interrupts [*]PCI-2.2 compliant, 32 bit 3.3 V PCI interface with 5 V tolerant inputs[/LIST] [*]Sophisticated PC2001-Compatible Mobile Power Management[LIST] [*]Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management [*]ACPI v2.0 and APM v1.2 Compliant [*]CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support [*]PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control [*]Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options, [*]suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up [*]Multiple suspend power plane controls and suspend status indicators [*]One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer [*]Normal, doze, sleep, suspend and conserve modes [*]Global and local device power control [*]System event monitoring with two event classes [*]Primary and secondary interrupt differentiation for individual channels [*]Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for [*]system wake-up [*]32 general purpose input ports and 32 output ports [*]Multiple internal and external SMI sources for flexible power management models [*]Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field [*]Thermal alarm on external temperature sensing circuit [*]I/O pad leakage control[/LIST] [*]Plug and Play Controller[LIST] [*]PCI interrupts steerable to any interrupt channel [*]Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio [*]Microsoft Windows XP TM , Windows NT TM , Windows 2000 TM , Windows 98 TM and plug and play BIOS compliant[/LIST] [*]Built-in NAND-tree pin scan test capability [*]0.22 um, 2.5 V, low power CMOS process [*]Single chip 27 x 27 mm, 1.0 mm ball pitch, 539 pin BGA[/LIST]I/O controller: WINBOND W83697HF I/O Controller with the following features [LIST] [*]PS/2 Keyboard and Mouse controller [*]Floppy disk controller supporting one FDD with 360 KB, 720 KB, 1.2 MB and 1.44 MB [*]2 serial ports, both 16C550 Fast UART compatible. [*]1 Parallel port supporting SPP (Standard parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Capabilities Port) modes [*]1 Fan controller[/LIST]Audio Chipset: Audio Subsystem for AC'97 processing using the Realtek ALC655 codec [LIST] [*]DirectSound AC'97 2.2 Audio [*]Inputs and Outputs: Stereo inputs for Line-in, CD audio, Auxiliary, mono inputs for microphone [*]Mixer Features: mixer with stereo for Line, CD audio, auxiliary, music synthesizer, digital audio (wave files), and mono for microphone and speaker phone [*]Features: 3D stereo enhancement for simulated surround, power management support [*]Stereo microphone input with integrated preamp for enabling a 2-channel mic array[/LIST][B][URL="http://www.oldskoolanthemz.com/forum/"][/URL]Connectors[/B] [LIST] [*]1 AGP slot with integrated retention mechanism [*]2 PCI +1 Combo PCI/CNR slot [*]1 DB9 serial port (COM A ) [*]1 Header serial port (COM B ) [*]1 DB15 VGA port [*]1 DB25 parallel port with SPP, ECP, EPP bidirectional modes [*]PS/2 keyboard and PS/2 mouse ports (not swappable) [*]6 USB 2.0; 2 rear ports + 2 front USB + 2 interne [*]1 mono microphone input (Mic-In) [*]1 Line-In [*]1 Line-Out [*]2 IDE connectors [*]1 Floppy connector [*]Panel connector [*]1 RJ45 connector[/LIST][B][URL="http://www.oldskoolanthemz.com/forum/"][/URL]Winbond BIOS Specifications[/B] [LIST] [*]Plug and Play [*]Advanced Configuration and Power Interface (ACPI) 1.0 [*]Advanced Power Management (APM) 1.2 [*]Y2K [*]PC 2001 [*]S3/S1 mode [*]Desktop Management Interface (DMI) [*]2 Mbits flash device [*]Language supported: English[/LIST][/LIST] [/QUOTE]
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